1. Field of the Invention
The present invention relates to self-test circuits used in digital systems and, more specifically, to a clocking system used with a self-test circuit.
2. Description of the Prior Art
Digital integrated circuits sometimes experience faults that interfere with circuit functionality. Most modern digital circuits of any complexity are subject to a battery of tests that are designed to detect and, sometimes, correct such faults. A wide variety of tests are used to detect faults, including functional testing in which a series of inputs is applied to a circuit and the outputs are compared to expected outputs. Functional testing is effective for simple circuits, but becomes unmanageably complex as the complexity of the circuit grows.
More complex circuits employ scan designs, in which latches distributed through out the circuit are connected to each other in series. Test data is scanned into the latches and then the circuit is operated for a short period. The data in the latches is then scanned out of the circuit and compared to expected data. A typical digital integrated circuit includes a plurality of latches that store logical states within the integrated circuit. A scan design employs latches that have both a functional mode and a scan mode. In the functional mode, data propagates through the latches and the logical elements associated with the latches during normal operation of the integrated circuit. In the scan mode, data is scanned serially from latch to latch so that the integrated circuit can be set to a predetermined state. The scan mode can be useful for initializing the integrated circuit and can be useful for testing the integrated circuit.
In a scanning self test, a set of data is scanned into a series of interconnected latches and the clock controlling the logic elements of the processor is asserted for a number of cycles. The data from the latches is then scanned out of the system and is compared to an expected result to determine if any of the logic elements includes a fault.
Many complex integrated circuits employ a level-sensitive scan design (LSSD). In an LSSD integrated circuit, a series of pairs of latches are distributed throughout the circuit. Each pair includes a first latch that is clocked by a first clock signal and a second latch, which receives the immediate data output of the first latch and that is clocked by a second clock signal that is different from the first clock signal.
In certain LSSD designs, special pulsing arrangements of the first clock signal and the second clock signal are employed to improve test coverage. These special pulses can simulate situations in which, for example, the timing of the second clock signal becomes skewed relative to the timing of the first clock signal.
Many integrated circuits employ a clock tree to distribute a central clock signal throughout the circuit. The clock tree includes a “root” clock that is repowered throughout a circuit by a plurality of splitters that power various “leaves” associated with individual LSSD latches. Some circuits employ local waveform generators at the leaves to create the special pulses used in testing. This approach has the disadvantage of being cumbersome and using a considerable amount of chip area.
Another design, referred to as at-speed structural test (ASST), employs a central test waveform generator/deskew circuit to generate the test pulses. In LSSD designs that require precise clock control, such as those with Logic Built-In Self-Test (LBIST), it is increasingly challenging to gate the clocks in a physical design and still pass static timing analysis requirements. Additionally, test coverage must be maintained to assure manufacturing quality. With clock root gating, it is possible to absorb most of the clock control logic into one central place, thereby gating the oscillator rather than attempting to gate a clock splitter at the leaf of the tree. This significantly improves static timing closure turn-around, as well as reduces the number of global routes needed for clock control logic and reduces the size of the multiple use leaf splitter. Through the use of an oscillator shaping logic, the oscillator at the root of the tree can be shaped and modified to produce many different styles of clocks for testing and function. With root gating, however, test coverage typically declines due to the lack of unique control at the splitter level. ASST accomplishes clock root gating by moving most of the oscillator control to a test waveform generator and a clock deskew unit (collectively referred to as “TWG-DESKEW”). However, the ASST structures are not available in certain earlier technologies. They also require a number of specially developed circuits.
Therefore, there is a need for a system that uses existing circuit design to get testing results comparable to the ASST approach.